European Patent Application No. EP-A-1193752 describes a method of forming localized SOI structures in a semiconductor wafer, wherein a dielectric (oxide) is formed over the entire surface of the substrate, then a polysilicon layer is deposited over the dielectric. Thereafter, the polysilicon layer and the dielectric layer are etched to correspond with the desired SOI region. Semiconductor material is deposited over the entire surface, leading to growth on the exposed regions of the wafer and growth on the polysilicon layer.
The semiconductor material is deposited by epitaxial growth which, in the region of the polysilicon layer, gives rise to a polycrystalline layer, in a thickness of 10 to 30 microns. This layer must be thermally treated in order to generate a monocrystalline region over the oxide. After provision of a cap oxide, the wafer is placed in a rapid thermal reactor to melt the polycrystalline layer and recrystallize it during the freezing step of the rapid thermal annealing. However, there is a likelihood that the thermal treatment will not yield a completely monocrystalline semiconductor region over the insulating layer: the polysilicon grains will grow but not necessarily disappear during the thermal treatment and it is not a straightforward matter to try and control the process to achieve the desired result.